In certain applications synchronization is required between multiple clock generating circuits. Each clock generating circuit nominally generates the same frequency within an error tolerance of the desired frequency. With the exception of the synchronization between the circuits, each circuit operates independently.
What is desired is a method and circuit for synchronizing a multiplicity of clock generating circuits whereby the starting point of the generation of the rising and falling edges are each determined by the majority vote of the states of the opposite edge from the system of circuits so that a reliably synchronized output clock signal can be provided.